A Reconfigurable Convolution-in-Pixel CMOS Image Sensor Architecture

The separation of the data capture and analysis in modern vision systems has led to a massive amount transfer between end devices cloud computers, resulting long latency, slow response, high power consumption. Efficient hardware architectures are under focused development enable Artificial Intelligence (AI) at resource-limited sensing devices. One most promising solutions is Processing-in-Pixel (PIP) scheme. However, conventional schemes suffer from low fill-factor issue. This paper proposes PIP based Complementary Metal-Oxide-Semiconductor (CMOS) sensor architecture, which allows convolution operation before column readout circuit significantly reduce overall consumption while improving resource utilization succeeding deep learning accelerator. simulation results show that proposed architecture could support computing efficiency up 3.37 TOPS/W 8-bit weight configuration, four times as after normalization. transistors required for each pixel only 3.5T, fill-factor.